Lucent-technologies MN10285K Manual de usuario Pagina 175
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On-Screen Display
ROM
Panasonic Semiconductor Development Company MN102H75K/F75K/85K/F85K LSI User Manual
174
Panasonic
Figure 7-11 Graphics ROM in the Four Color Modes (16W x 16H Tiles)
ROMEND−80×N+1
ROMEND−180
ROMEND−160
ROMEND−140
ROMEND−120
ROMEND−100
ROMEND−E0
ROMEND−C0
ROMEND−A0
ROMEND−80
ROMEND−60
ROMEND−40
ROMEND−20
ROMEND
Required bytes
per tile
2 colors
N × 4 − 1
.
.
.
0C
0B
0A
09
08
07
06
05
04
03
02
01
00
32 bytes
See fig.7-15
128 bytes
Graphic Tile Codes
8 colors
N × 4/3 − 1
.
.
.
04
03
02
01
00
96 bytes
See fig.7-13
4 colors
N × 2 − 1
.
.
.
06
05
04
03
02
01
00
64 bytes
See fig.7-14
16 colors
N − 1
.
.
.
03
02
01
00
128 bytes
See fig.7-12
N is a
multiple of 3.
- MN102H75K/F75K/85K/F85K 1
- LSI User’s Manual 1
- Contents 4
- List of Tables 10
- List of Figures 12
- About This Manual 17
- Related Documents 18
- 1 General Description 19
- MN102H Series Features 21
- 1.3 MN102H Series Description 22
- General Description 24
- CPU Core 26
- 1.4 General Specifications 27
- 1.5 Block Diagram 29
- 1.6 Pin Descriptions 31
- ■ Connection the PLL circuit 35
- 1.7.1 Description 36
- 2 Interrupts 38
- 2.2 Interrupt Setup Examples 41
- ———————ID 45
- — LV2 LV1 LV0 — — — IE 45
- ———IR———ID 46
- 3.1.1 Description 73
- 3.3 CPU Control Register 77
- All passages below assume a 78
- of 24 MHz 78
- 4.2 8-Bit Timer Features 79
- 4.4 8-Bit Timer Timing 82
- Timer 0 underflow 84
- 4.7 16-Bit Timer Description 89
- 4.8 16-Bit Timer Features 90
- 4.10 16-Bit Timer Timing 91
- New value written 92
- to CCRB 92
- Change reflected in 92
- 16-Bit Timer Setup Examples 100
- Panasonic 100
- A. Chip Level 102
- B. Block Level 102
- Interrupt B 107
- TM3CA is the larger value 111
- (TM5LP must be 0.) 112
- TM5IA ↑ 1 ↓ 0 ↑ 0 ↓ 1 114
- TM5IB 0 ↑ 1 ↓ 1 ↑ 0 ↓ 114
- TM5IA ↓↑ 117
- TM5IB 11 117
- Controller 118
- Using Timer 5 121
- 5 Serial Interfaces 128
- 5.3.2 UART Mode Connections 129
- C Mode Connection 129
- 5.4 UART Mode Baud Rates 130
- 5.5 Serial Interface Timing 130
- 5.5.2 UART Mode Timing 131
- Interface 0 135
- 5.6.4 Setting Up I 138
- 5.6.5 Setting Up I 140
- 6 Analog-to-Digital Converter 144
- 6.3 Block Diagram 145
- 6.4 A/D Conversion Timing 145
- 6.5 ADC Setup Examples 148
- A/D Conversion 149
- Conversion 151
- Interrupts 151
- R << 8kΩ 153
- or 153
- 7 On-Screen Display 154
- In closed-caption mode: 154
- 7.3 Block Diagram 155
- 7.5.1 OSD Clock 157
- 7.5.3 Multi-Layer Format 157
- 7.5.4 Output Pin Setup 158
- 7.5.6 VRAM 158
- Set CHP, CVP, GHP, and GVP 159
- Display start position 161
- 7.7 Display Setup Examples 162
- On-Screen Display 163
- 7.8.1 VRAM Operation 166
- 7.8.2 VRAM Organization 170
- 7.9.1 ROM Organization 173
- In 16-color mode, each tile 173
- Graphic Tile Codes 175
- 7.10 Setting Up the OSD 179
- Setting Up the OSD 181
- Internal DAC 184
- 7.10.2 Text Layer Functions 185
- Box shadowing (black) 186
- Box shadowing (white) 186
- Caption mode 187
- Underlining 187
- 7.10.3 Display Sizes 188
- × 1 × 2 × 3 × 4 189
- RGB, YM, YS 190
- 7.11 DMA and Interrupt Timing 192
- (with 4-MHz osc.) 194
- CDE 200
- 7.14.1 Block Diagram 202
- 7.14.2 Description 202
- 7.15 OSD Registers 204
- 00 1 H scan line Reserved 206
- 8 IR Remote Signal Receiver 217
- 8.2 Block Diagram 218
- 8.3.1 Operating Modes 219
- 8.3.2 Noise Filter 219
- 8.3.3 8-Bit Data Reception 220
- 5-/6-bit format HEAMA format 221
- 8.3.5 Generating Interrupts 222
- Bit:76543210 224
- Reset:00000000 224
- 9 Closed-Caption Decoder 228
- 9.3 Functional Description 229
- 9.3.2 Clamping Circuit 230
- 9.3.3 Sync Separator Circuit 231
- Closed-Caption Decoder 232
- 9.3.4 Data Slicer 234
- Valid range: x’00’ to x’FF’ 239
- 341.3 µs (2 ms for SLOW mode) 250
- 1.33 µs (8 µs for SLOW mode) 250
- High level 250
- Low level 250
- 10.2 Block Diagram 251
- 10.3 PWM Data Registers 251
- 11 I/O Ports 252
- I/O Ports 253
- SIFSEL0 (PCNT0 x’FF90’ bp12) 279
- Enable PWM (set PCNT1 bit 1 286
- 12 ROM Correction 289
- 12.2 Block Diagram 290
- ROM Correction 293
- C Bus Controller 294
- 13.2 Block Diagram 297
- 13.3 Functional Description 297
- 13.4 Setting Up the I 299
- C Bus Connection 299
- C bus interface 300
- C Interface Setup Examples 301
- (slave address) 302
- Transmitter 303
- C Bus Interface Registers 305
- 14 H Counter 308
- ≥ 245 ns t 309
- ≥ 200 ns 309
- H Counter Operation 310
- H Counter 312
- Appendix ARegister Map 313
- Register Map 314
- B.1 Description 317
- B.2 Benefits 318
- Onboard serial writer 320
- Serial communication 320
- 16-bit microcontroller 320
- Television set 320
- Serial Programming 324
- Reset start 327
- Start serial writer 327
- Execute user 327
- Write 0s to entire memory 329
- Write user program 329
- Erase routine 329
- Sales office C Latest version 330
- I/O ports 331
- 84-pin QFP 331
- 64-Pin SDIP 332
- Top View 332
- Third-party 335
- PROM writer 335
- MN102HF75K 335
- Adaptor socket for MN102HF75K 335
- SALES OFFICES 338
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